This invention grew out of needs associated with bottom gated thin film transistors (TFTs) utilizing conductive polysilicon as the gate material. In these and other semiconductor applications, it is desirable to provide a smooth surface, high conductivity, low topology conductive interconnect utilizing an outer layer of polysilicon. For example in a bottom gated TFT, the outer gate surface is ideally as smooth as possible to minimize asperities that can undesirably cause high electric is field regions in the subsequently thin deposited dielectric layer. These high field regions can later cause early breakdown voltages of the gate dielectric.
The conductive bottom gate of a thin film transistor typically comprises a line of polycrystalline material, usually polysilicon. While electrically conductive, conductively doped polysilicon has considerably higher resistance than other possible materials, such as metal. Polycrystalline materials are, however, materials of choice due to their ability to withstand subsequent high temperature processing steps inherently found in semiconductor wafer fabrication. Conductivity in a polysilicon line can be increased by increasing the thickness of the line or by maximized doping with conductivity enhancing impurities. Typically the polysilicon is provided with its maximum practical doping, however, and increasing thickness undesirably increases topology and therefor reduces process margins at subsequent photo and etch steps.
Another prior art method of increasing the conductance in a polysilicon line is to provide a layer of metal silicide on the outer top surface of the line. Such materials have considerably higher conductivity than conductively doped polysilicon, thereby maximizing the overall conductance of a polysilicon line. This technique is impractical, however, where the outer surface of the polysilicon line is to be utilized as a gate electrode for a thin film transistor. Most desirably, the interface between the conductive line and gate dielectric constitutes polysilicon having a very smooth surface interface between the gate dielectric and line. Provision of silicide would defeat this purpose.
It would be desirable to overcome these and other problems associated with the prior art processes and constructions. While the invention was motivated by processes associated principally with TFT formation, the artisan will appreciate that aspects of the invention have applicability to other methods and constructions. The invention is intended to be limited only by the accompanying claims appropriately interpreted in accordance with the Doctrine of Equivalents.